Charge coupled devices, often referred to as "CCDs", are used in various fields such as solid state imaging, analog signal processing, and memories for both analog and digital signals. An interline CCD sensor has an image sensing area, and at least one horizontal shift register. The image sensing area has independent photosites that convert incident light into electrons which are transferred into vertical shift register cells adjacent to the photosites upon application of a clock signal. A clock pulse employed on the vertical registers has three potential levels. The first and second clock levels are alternately applied to the vertical CCD to transfer charge along the vertical CCD and from the vertical CCD to a horizontal CCD that is adjacent to the image sensing area. The third level on the clock assists the movement of charge from the photo cites to the vertical CCD.
Horizontal clocks move the charge from the horizontal CCD to a floating diffusion. A buffer amplifier on the CCD sensor is used to sense the voltage of the floating diffusion on which the charge from horizontal shift registers is transferred and provides an output signal from the device to external circuits. The floating diffusion is reset before the charge is transferred by the next horizontal clock cycle. The output of the output amplifier is processed by a sample and hold circuit and compared to the precharge level of the floating diffusion. This difference is proportional to the intensity of the light falling on the object and will eventually become video.
In order to construct a video camera, the number of pixels per line and the rate of clocking of the pixels and the number of lines per frame and the rate of clocking of the lines should be controlled. This control is normally accomplished by timing logic external to the sensor. The output from these cameras can easily be seen on a standard TV monitor if the clocking time of the sensor abides by the NTSC standards. The designers of the sensors are well aware of this fact and hence they predetermine the number of pixels and the number of lines on the sensor to meet the standards. The number of pixels per line, the number of lines on the sensor, the clocking speed of pixels and the clocking speed of lines is normally based on a) the frame rate at which the sensor is emptied, and b) the resolution of the image the application demands. For NTSC standards the number of pixels per line is based on the subcarrier frequency. The clocking speed of pixels is normally an integral multiple of the subcarrier frequency which is 3.5795 MHz. Thus the clocking speed of pixels for sensors designed for NTSC standards generally has been 3.5795 MHz, 7.1591 MHz, 10.7386 MHz or 14.3182 MHz depending on the resolution of the sensor. The number of lines for all NTSC standard sensors has also been fixed.
In order to satisfy the timing requirements, many companies typically develop a full custom timing chip in parallel with the development of a sensor device. The investment for the development of this timing chip represents a considerable cost in addition to the development of the sensor. There remains a need within the prior art for a sensor device that alleviates this additional cost.